Planar VLS grown GaAs nanowire array based HEMTs

In order to suppress short channel effects as gate length of field effect transistors (FETs) continues to downscale, multi-gate FETs and nanowire FETs (NW-FETs) are poised to replace traditional planar devices. Top-down defined NW-FETs are susceptible to etching damages and the size of which is limited by lithography. Bottom-up self-assembled III-V NWs are particularly interesting because of the simplicity in processing which doesn´t require lithography and chemical etching, potentially smaller feature sizes than defined by lithography and inherent high carrier mobility. However, there are three main challenges of realizing bottom-up grown NW-FET based circuits including: controllability of NW growth direction and positioning; uniformity of NW electrical property; and compatibility with planar processing.