Title :
Proceedings. The European Conference on Design Automation (Cat. No.92TH0414-3)
Abstract :
The following topics were dealt with: future of VLSI CAD; system-level synthesis; design methodology management; programmable devices synthesis; formal languages, synthesis and verification; functional-level and logic simulation; combinatorial logic synthesis; testing and layout verification; built in self test; datapath synthesis and design representation; switch level and circuit simulation; sequential circuit synthesis; application specific CAD for system design; delay testing and test data computation; high level synthesis; placement and routing; testing processors and synthesis for test; timing and switch level verification; data management techniques; test pattern generation and fault generation; binary decision diagrams and functional abstraction; analogue design and simulation; scheduling; layout synthesis; and testing for mixed analogue and digital
Keywords :
VLSI; application specific integrated circuits; circuit CAD; circuit analysis computing; circuit layout CAD; configuration management; delays; digital integrated circuits; formal verification; integrated circuit testing; logic CAD; logic arrays; logic testing; minimisation of switching nets; specification languages; VLSI CAD; analogue design; binary decision diagrams; circuit simulation; combinatorial logic synthesis; data management techniques; datapath synthesis; delay testing; design methodology management; design representation; fault generation; formal languages; functional abstraction; high level synthesis; layout synthesis; layout verification; logic simulation; placement; programmable devices synthesis; routing; sequential circuit synthesis; switch level verification; system design; system-level synthesis; test data computation; test pattern generation; timing;
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels, Belgium
Print_ISBN :
0-8186-2645-3
DOI :
10.1109/EDAC.1992.205874
