Hydrodynamic simulations of a nanoscale RingFET

Scaling down the width of conventional planar FETs can create significant leakage currents as a result of trapped positive charges in the side interfaces (Figure 1) causing weak inversion in the channel. Trap induced leakage currents have been previously addressed with FinFET, body-accumulated, and gate wrap-around designs. In this study, we propose a compact, cylindrical FET design, the RingFET, which effectively eliminates any side interface regions. The RingFET is composed of concentric regions which form the source, drain, poly-silicon gate, channel, and aluminum metal contacts. Figure 2(a) shows a top view cross section of the implanted regions in the body of the n-channel RingFET where the red rings are n-type (Arsenic doped) and the blue ring is p-type (Boron doped). Hydrodynamic simulations using Synposys Sentaurus TCAD software are preformed to analyze the performance of nanoscale RingFETs. The RingFET´s cylindrical geometry allows for 2D rotationally symmetric simulations which significantly decrease computational time as compared to 3D simulations. Figure 2(b) shows the simulated radial cross section where an effective width of the device is defined as the average radius of the channel, W_EFF = 2π·R_W.