The impact of abstract data types on the digital system description and simulation environments

Over the years, many features of programming languages have been adopted in the design of hardware description languages (HDLs). The incorporation of facilities to support building abstract data types in HDLs is examined. In particular, the use of abstract data types in VHDL is considered in the description and simulation of digital systems. Furthermore, the user-interface of a VHDL simulator is considered and the question `are the benefits of abstract data types defeated by a primitive simulator user interface?´ is asked. Finally, an extended VHDL package is shown that provides the designer with a mechanism for extending the user interface of an interactive simulator