Accurate delay models for ECL logic synthesis

The usage of logic synthesis tools for ECL logic has been questionable, among other reasons, because of the discrepancy between the simple, computationally efficient models required by synthesis and the more and more sophisticated models required for accurate simulation. The paper demonstrates that with appropriate choice of modelling parameters, it is possible to map an existing ECL simulation library to a synthesis library with errors below 1%. The authors review the basic delay calculation algorithms provided by a prominent commercial ECL Logic Synthesis tool (Synopsys). They show how delay data is generated by their proprietary delay calculator DECAL. They develop a simplification scheme that enables the algorithms given in Synopsys to produce accurate results. Finally, they present some results on accuracy