DocumentCode
3098410
Title
A parallel hierarchical design rule checker
Author
Hedenstierna, Nils ; Jeppson, Kjell O.
Author_Institution
Dept. of Solid-State Electron., Chalmers Univ. of Technol., Goteborg, Sweden
fYear
1992
fDate
16-19 Mar 1992
Firstpage
142
Lastpage
146
Abstract
The halo algorithm, a novel and efficient algorithm for hierarchical design-rule checking (DRC) has been modified for parallel processing. Like the sequential halo algorithm, the parallel version identifies repeated subcell interactions and checks them only once thereby improving performance substantially. Inverse layout trees are used to handle interacting primitives hierarchically. The algorithm has been implemented on workstations connected by a local area network and on a shared memory multicomputer
Keywords
VLSI; circuit analysis computing; circuit layout CAD; formal verification; parallel algorithms; VLSI circuits; halo algorithm; inverse layout tree; local area network; parallel hierarchical design rule checker; parallel processing; shared memory multicomputer; subcell interactions; Concurrent computing; Data mining; Data structures; Local area networks; Parallel processing; Solid state circuits; Testing; Very large scale integration; Wires; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location
Brussels
Print_ISBN
0-8186-2645-3
Type
conf
DOI
10.1109/EDAC.1992.205910
Filename
205910
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