A reconfigurable and scalable architecture for security coprocessor

Security coprocessor can offer special and customized security guarantee for computing and communication system. In most of the application fields, the coprocessor should be small-area, low-power, low-cost and high-availability, which can not only provide various candidate encryption algorithms, but also with acceptable performance according to the application requirement. In the view of this context, we propose a kind of new system architecture for security coprocessor based on reconfiguration, scalability and tightly coupled structure ideas, which can achieve various encryption operations with easy upgrade and reconfiguration. On the other hand, the security coprocessor can also mitigate the contention of data bus and raise the transfer data rate through the optimized internal data bus network. The new architecture can greatly reduce the area and power consumption of the security coprocessor, and improve the adaptability, flexibility and security of the whole system. At the end of this paper, a security coprocessor is implemented in 0.13-μm CMOS technology to verify the ideas of the paper, where different encryption algorithms are realized through changing the content of instruction set registers. The core area of the improved security module is 56 K gates at 100 MHz with an average power of 83 mW. Comparing with traditional work, we achieve equal security function with lower power, smaller size and easier reconfiguration.