Title :
Exploiting hierarchy in a cache-based switch-level simulator
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana-Champaign, IL, USA
Abstract :
The article presents a caching method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a factor of two. While caching may require additional memory it is shown how the structural hierarchy can be exploited to quickly identify subnetworks computing identical functions, merge their cache tables and significantly reduce the memory requirements
Keywords :
circuit analysis computing; digital integrated circuits; dynamic programming; cache tables; cache-based switch-level simulator; structural hierarchy; subnetwork evaluation; Analytical models; Boolean functions; Circuit simulation; Computational modeling; Costs; Data structures; Databases; Digital circuits; Dynamic programming; Switching circuits;
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
DOI :
10.1109/EDAC.1992.205924