A novel in-process wafer-level screening technique for CMOS devices

Author

Yoshii, I. ; Hama, K. ; Hazama, H. ; Kamijo, H. ; Ozawa, Y.

Author_Institution

Toshiba Microelectronics Corp., Kawasaki, Japan

fYear

1997

fDate

13-16 Oct 1997

Firstpage

86

Lastpage

91

Abstract

We have developed a novel in-process wafer-level screening technique to eliminate CMOS device infant mortality due to gate oxide defects. Using this technique, it is possible to stress all gate oxides simultaneously at an arbitrary high voltage for both n-channel and p-channel transistors. This paper describes the details of the screening method and its application to the standard 0.8 μm CMOS logic technology. The result shows that early TDDB failures are significantly reduced by this technique

Keywords

CMOS logic circuits; dielectric thin films; electric breakdown; integrated circuit reliability; integrated circuit testing; integrated circuit yield; production testing; 0.8 micron; CMOS device infant mortality; CMOS devices; CMOS logic technology; HV gate oxide stressing; Si; SiO₂-Si; early TDDB failures; gate oxide defects; in-process wafer-level screening; in-process wafer-level screening technique; n-channel transistors; p-channel transistors; Breakdown voltage; CMOS process; CMOS technology; Electric breakdown; Fabrication; Integrated circuit interconnections; Logic devices; MOS devices; Stress; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 1997 IEEE International

Conference_Location

Lake Tahoe, CA

Print_ISBN

0-7803-4205-4

Type

conf

DOI

10.1109/IRWS.1997.660293

Filename

660293