DocumentCode :
3098769
Title :
An alternative to fault simulation for delay-fault diagnosis
Author :
Girard, P. ; Landrault, C. ; Pravossoudovitch, S.
Author_Institution :
Lab. d´´Inf. de Robotique et de Microelectron. de Montpellier, Univ. de Montpellier II Sci. et Tech. du Languedoc, France
fYear :
1992
fDate :
16-19 Mar 1992
Firstpage :
274
Lastpage :
279
Abstract :
Delay testing is a test procedure to verify the timing performance of manufactured digital circuits. A diagnosis process is often implemented after the detection of a fault in a circuit. Unfortunately, existing methodologies for locating delay defects on digital circuits have shown certain deficiencies. A new method for delay fault diagnosis, based on critical path tracing from a symbolic simulation, is presented. This method needs to consider only the fault-free circuit and provides perfectly reliable results. It does not require timing evaluations and can be very accurate
Keywords :
delays; fault location; integrated circuit testing; integrated logic circuits; logic testing; critical path tracing; delay defect location; delay testing; delay-fault diagnosis; digital circuits; fault detection; fault-free circuit; symbolic simulation; timing performance verification; Circuit faults; Circuit simulation; Circuit testing; Delay; Digital circuits; Electrical fault detection; Fault detection; Fault diagnosis; Manufacturing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
Type :
conf
DOI :
10.1109/EDAC.1992.205938
Filename :
205938
Link To Document :
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