Title :
Signature analysis under a delay fault model
Author :
Saxena, Jayashree ; Pradhan, Dhiraj K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
A framework for aliasing under a delay fault model is presented. First, error patterns under this fault model are characterized. Through this, specific error patterns that can occur are identified. Based on this, it is shown that using a model similar to the equiprobable model, the aliasing probability under certain conditions converges to 2-m for delay faults as well. A closed form expression for aliasing under an independent error model is also derived. This expression is shown to yield better theoretical estimates of the aliasing probability
Keywords :
VLSI; built-in self test; delays; error analysis; fault location; integrated circuit testing; integrated logic circuits; logic testing; probability; aliasing probability; closed form expression; delay fault model; equiprobable model; error patterns; signature analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; DH-HEMTs; Delay; Estimation theory; Very large scale integration; Yield estimation;
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
DOI :
10.1109/EDAC.1992.205940
