Title :
On achieving zero aliasing for modeled faults
Author :
Pomeranz, Irith ; Reddy, Sudhakar M. ; Tangirala, Ravi
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
Methods for test-data compression ensuring zero aliasing in logic circuits are described. Aliasing occurs when due to loss of information during compression of the output response, a faulty circuit appears to be fault free. Zero aliasing is guaranteed for a given set of target faults, detected by the test set applied to the circuit. The inability of probabilistic analysis of aliasing to predict coverage of target faults is thus alleviated. Experimental results are presented to support the practicality of the methods proposed in ensuring zero aliasing
Keywords :
fault location; integrated circuit testing; logic circuits; logic testing; faulty circuit; logic circuits; modeled faults; output response; probabilistic analysis; test-data compression; zero aliasing; Built-in self-test; Circuit faults; Circuit testing; Cities and towns; Electrical fault detection; Fault detection; Hardware; Linear feedback shift registers; Logic circuits; Logic testing;
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
DOI :
10.1109/EDAC.1992.205941
