A realization algorithm of asynchronous circuits from STG

The synthesis of asynchronous circuits from the behavioral descriptions in signal transition graphs (STG) is studied. A new realization algorithm is proposed to synthesize asynchronous circuits directly from STGs and thereby to maintain the problem size proportional to the signal number only. In previous methods, the state diagram was involved in the synthesis, which has a worst-case size exponential to the signal number. Based on the transitive lock relation, the authors´ realization algorithm is shown to realize a one-level circuit when the given STG is L^t2. The simple one-level realization ensures that the realized circuit is hazard-free under the gate delay model without any post-realization modification