Title :
A 0.1–2 GHz CMOS RF front-end for Software-Defined Radio applications
Author :
Lei, Xuemei ; Wang, Zhigong ; Wang, Keping
Author_Institution :
Sch. of Electron. & Inf. Eng., Inner Mongolia Univ. Daxuexilu, Hohhot, China
Abstract :
In this paper, A Software-Defined Radio (SDR) RF front-end is presented that contains LNA, mixers, VGAs, and frequency synthesizer, supporting various wireless communication standards in 0.1-2 GHz while guaranteeing a power/performance trade-off at any time. The circuit is fabricated in a 0.18 μm RF CMOS technology with 1.8 V supply voltage. Simulated result shows that the receive path achieves a Noise Figure of 3.8 dB at 160 MHz and 5.5 dB at 2 GHz. The Output-referred 3rd-order Intercept Point (OIP3) is high up to 21.3 dBm at 800 MHz. The voltage gain of the front-end is between 16-44 dB. The phase mismatch of LO quadrature signals is lower than 3°. It consumes 78.8 mW at the 1.8V supply.
Keywords :
CMOS integrated circuits; frequency synthesizers; low noise amplifiers; mixers (circuits); software radio; CMOS RF front-end; LNA; VGA; frequency 0.1 GHz to 2 GHz; frequency 160 MHz; frequency 2 GHz; frequency 800 MHz; frequency synthesizer; gain 16 dB to 44 dB; mixers; noise figure 3.8 dB; noise figure 5.5 dB; output-referred 3rd-order intercept point; power 78.8 mW; size 0.18 mum; software-defined radio applications; voltage 1.8 V; wireless communication standards; CMOS integrated circuits; Frequency synthesizers; Gain; Linearity; Mixers; Radio frequency; Wideband; LNA; Mixer; SDR; VGA;
Conference_Titel :
Computer Research and Development (ICCRD), 2011 3rd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-61284-839-6
DOI :
10.1109/ICCRD.2011.5764193
