A clock net routing algorithm for high performance VLSI

Presents a new algorithm, called FSTM (`feasible segment tree method´), for the clock net routing of high performance VLSI designs. To avoid the clock skew, FSTM constructs a binary tree such that for each internal vertex of the tree, the cardinality of its sub-trees are balanced and the distances to its children are equal. The authors evaluate their results in terms of wire length and delay time (by the SPICE simulator). Experiments show that the clock net trees routed by FSTM achieve 13% in wire length, 3% in maximum delay and 36% in clock skew improvement over previously published results