Title :
Synonym hit RAM; a 500 MHz 1.5 ns CMOS SRAM macro with 576 b parallel comparison and parity check functions
Author :
Suzuki, T. ; Higeta, K. ; Fujimura, Y. ; Nambu, H. ; Yamagata, R. ; Yamaguchis, K.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
Recently, the capacity of first-level caches has increased to 32-64kB, improving microprocessor performance. In a large-capacity cache that operates at high speed, address translation delay is not negligible and a virtual cache without address translation is essential. As cache size increases, synonyms will be a serious problem because of ambiguity in address translation. The synonym hit RAM overcomes this problem. This RAM features a 500MHz CMOS SRAM macro with 576b parallel comparison and parity check functions. Use of a source-coupled logic (SCL) circuit for the comparator is essential to obtaining 1.5ns access time for comparison.
Keywords :
CMOS memory circuits; 1.5 ns; 500 MHz; CMOS SRAM macro; access time; address translation; address translation delay; first-level caches; large-capacity cache; parallel comparison; parity check functions; source-coupled logic; synonym hit RAM; virtual cache; Added delay; CMOS logic circuits; Circuit testing; Laboratories; Logic circuits; Microprocessors; Operating systems; Parity check codes; Random access memory; Read-write memory;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672517
