MOSFET mobility model at nanoscale including temperature effects

The utility of the circuit simulators as a tool for the design and analysis of VLSI circuits depends on the adequacy of the device model being used in the simulator. In practical, the adequacy and simplicity (computational efficiency) of the model directly affects the corresponding accuracy and speed of simulation. It has been found that the for the large circuits the MOSFET Model evaluation accounts for a large percentage (up to 80%) of the total analysis time. Further, the effects of temperature on materials and devices have been of great interest throughout the history of semiconductor research. The operation of MOSFET at low and a high temperature is of quite interest. Lowering the operating temperature can help in achieving the desired increase in performance. In addition, lower temperatures increase the current drive of a MOSFET via increased mobility of the electrons and holes in the device. Equally importantly, the parasitic resistances of the device and the interconnect decrease as temperature decreases. As the dimensions are shrinking, e.g. the channel length reduces to nano scales in MOSFET, the various device parameters are also affected by the introduction of different short as well as narrow channel effects. One of the most important parameter, here we are going to work on, is the MOSFET mobility at nanoscales. How the mobility is going to be affected by the various quantum effects pronounced at low dimensions and what is the effect of mobility at various temperatures. My work includes the mobility model which is empirically fitted for a wide range of temperatures including the various short as well as narrow quantum effects.