Heuristics for computing robust tests for stuck-open faults from stuck-at test sets

Author

Chakravarty, Sreejit

Author_Institution

Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA

fYear

1992

fDate

16-19 Mar 1992

Firstpage

416

Lastpage

420

Abstract

Heuristics for identifying stuck-open faults for which a robust test can be computed from any stuck-at-test set are presented. Experimental results show that these heuristics can be used to compute robust tests for a large percentage of stuck-upon faults. Since stuck-at test generation is considerably faster than computing a robust test-pair for a given stuck-open fault, these heuristics can be used to speed up the process of computing robust tests for stuck-open faults. The author addresses the problem of computing robust tests for stuck-open faults in static CMOS circuits consisting of NOT, NAND, NOR, AND and OR gates

Keywords

CMOS integrated circuits; automatic testing; circuit analysis computing; fault location; integrated circuit testing; logic gates; heuristics; logic gates; robust tests; static CMOS circuits; stuck-at test sets; stuck-open faults; test generation; CMOS process; Circuit faults; Circuit testing; Computer science; Delay estimation; Electrical fault detection; Fault detection; Fault diagnosis; Manufacturing; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1992. Proceedings., [3rd] European Conference on

Conference_Location

Brussels

Print_ISBN

0-8186-2645-3

Type

conf

DOI

10.1109/EDAC.1992.205968

Filename

205968