Title :
An improved low-power clock-gating pulse-triggered JK flip-flop
Author :
Xianghong, Zhao ; Jiankang, Guo ; Guanghui, Song
Author_Institution :
Ningbo Inst. of Technol., Zhejiang Univ., Ningbo, China
Abstract :
In this paper, an improved clock-gating pulse-triggered JK Flip-flop (CG-PT-JKFF) for low-power requirements is presented. It is based on clock-gating technique, and power consumption is reduced because redundant internal switching activities are eliminated. When probability of activities of the flip-flop is 25%, the improved flip-flop can save up to 41% of the Power.
Keywords :
clocks; flip-flops; logic gates; low-power electronics; activity probability; clock-gating pulse-triggered JK flip-flop; low-power requirement; power consumption; redundant internal switching activity; Clocks; Flip-flops; Generators; CMOS; JK flip-flop; clock-gating; low-power; pulse-triggered;
Conference_Titel :
Information Networking and Automation (ICINA), 2010 International Conference on
Conference_Location :
Kunming
Print_ISBN :
978-1-4244-8104-0
Electronic_ISBN :
978-1-4244-8106-4
DOI :
10.1109/ICINA.2010.5636463
