DocumentCode :
3099273
Title :
Efficient test set evaluation
Author :
Wunderlich, Hans-Joachim ; Warneck, Manx
Author_Institution :
Univ. GHS Siegen, Germany
fYear :
1992
fDate :
16-19 Mar 1992
Firstpage :
428
Lastpage :
433
Abstract :
The fault coverage obtained by a set of test patterns is usually determined by expensive fault simulation. Even when using fault dropping techniques, fault simulation provides more information than actually needed. For each fault, the pattern is determined which detects this fault first. This is mainly redundant information if diagnosis is not required. One can dispense with this high resolution and restrict interest to the set of faults which is detected by a set of patterns. It is shown theoretically and practically that this information is obtainable in an highly efficient way
Keywords :
automatic testing; circuit analysis computing; digital simulation; fault location; integrated circuit testing; efficiency; fault coverage; fault simulation; integrated circuit testing; redundant information; test patterns; test set evaluation; Analytical models; Circuit faults; Circuit simulation; Computational modeling; Concurrent computing; Fault detection; Optimization methods; Partitioning algorithms; Switches; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
Type :
conf
DOI :
10.1109/EDAC.1992.205970
Filename :
205970
Link To Document :
بازگشت