Extended defects that affect carrier lifetime in high blocking voltage SiC epilayers

High carrier lifetime (>;1 μs) is essential to realize high power silicon carbide bipolar devices in order to obtain conductivity modulation in the thick voltage blocking layers [1]. To achieve low on-state resistance a carrier lifetime of >;5 μs is required for 10 kV blocking layers and >;20 μs for 20 kV blocking layers [2]. However typical lifetime for SiC epilayers is still less than 1 μs that is a few orders lower than silicon. Recently significant work has been done to improve the carrier lifetime in SiC by various oxidation and annealing techniques [3,4] that showed lifetime as high as 18.5 μs. The lifetime improvements have been attributed to recombination of extrinsically introduced carbon interstitials with carbon vacancies, which in turn lower the Z_1/2 center. However, during epigrowth and also in the high temperature steps extended defects are formed in the epilayers, which also impact the lifetime adversely. Previously, lifetime degradation has been shown in relatively thin epilayers resulting from in grown stacking faults, low angle boundaries, micropipes, and carrot defects [5,6]. In this work, we report on the influence of various other extended defects on carrier lifetime such as half loop arrays, slip bands, morphological defects, and single stacking faults in thick epitaxial layers.