DocumentCode
3099520
Title
Scheduling between basic blocks in the CADDY synthesis system
Author
Gutberlet, P. ; Rosenstiel, W.
Author_Institution
Comput. Sci. Res. Center, Karlsruhe Univ., Germany
fYear
1992
fDate
16-19 Mar 1992
Firstpage
496
Lastpage
500
Abstract
In `high level´ IC synthesis, basic blocks are caused by the control schemes and the block structure of the specification language (branches, loops). These schemes must be considered by the construction of the controller. A method is presented to handle the basic blocks in a more flexible way which allows one to move operations between basic block boundaries. The goal is to improve the number of control steps of the circuit under fixed hardware resources
Keywords
circuit CAD; scheduling; specification languages; CADDY synthesis system; basic blocks; block structure; circuit; control schemes; control steps; fixed hardware resources; specification language; Automatic control; Circuit synthesis; Computer science; Control system synthesis; Costs; Hardware; High level synthesis; Processor scheduling; Specification languages; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location
Brussels
Print_ISBN
0-8186-2645-3
Type
conf
DOI
10.1109/EDAC.1992.205985
Filename
205985
Link To Document