DocumentCode :
3099557
Title :
Automatic jog insertion for 2D mask compaction: a global optimization perspective
Author :
Martineau, J.-L. ; Bois, G. ; Cerny, E.
Author_Institution :
Dept. d´´Inf. et de Recherche Oper., Montreal Univ., Que., Canada
fYear :
1992
fDate :
16-19 Mar 1992
Firstpage :
508
Lastpage :
512
Abstract :
A novel approach is presented to global optimization in 2D symbolic layout compaction based on `branch and bound´ optimization, including automatic overconstraint resolution and jog insertion. The main characteristics are: an efficient generation in 2D of a nearly irredundant set of simple X and Y, diagonal and user constraints; incremental event-driven longest path calculation with positive cycle detection and identification simultaneously in the X and Y constraint graphs; jog insertion based on LP information from both graphs; and incremental update of constraints based on local information within the graphs whenever a diagonal constraint is relaxed or a jog is inserted. As both dimensions are processed concurrently from a global perspective, the method shows promising results
Keywords :
circuit layout CAD; optimisation; 2D symbolic layout compaction; LP information; automatic overconstraint resolution; branch and bound; constraint graphs; global optimization; incremental event-driven longest path calculation; incremental update; jog insertion; local information; nearly irredundant set; novel approach; positive cycle detection; user constraints; Character generation; Circuits; Compaction; Constraint optimization; DH-HEMTs; Law; Legal factors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
Type :
conf
DOI :
10.1109/EDAC.1992.205988
Filename :
205988
Link To Document :
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