Analysis of via-void generation mechanism for giga-bit-scale DRAM

The via-void generation mechanism in a high density DRAM with high temperature stress was investigated. The reaction of Al with the wetting layer is one of the key factors creating the microstructure. Stress enhancement after the interconnection process enhances the volume shrinkage of the interconnect and finally generates an observable via-void. By ABAQUS simulation, the depth of via formation, passivation material and thickness, and thermal budget of the alloying process were also shown to be the major stress-influencing factors. The void-free, high reliability gigabit-scale DRAM was realized when the Al reaction and interconnection related stress was minimized