Title :
Towards automatic parallelization of “for” loops
Author :
Bhat, Amit G. ; Babu, Meghana N. ; Anala, M.R.
Author_Institution :
Dept. of CSE, R.V. Coll. of Eng., Bangalore, India
Abstract :
An effective mechanism to improve the performance of a computing device is to include multiple processing units on a single integrated die. To exploit the performance gain of this mechanism, developing parallel programs is necessary. However, some existing programs are developed for serial execution and manual redesign of all such programs is tedious. Hence, automatic parallelization of existing serial programs is advantageous. One of the methods to execute programs in parallel is to make use of parallel computing platforms. With myriad number of parallel computing platforms, abstracting them from the developer is propitious. In this paper we propose an algorithm which is capable of detecting potential `for´ loops in C code that can be parallelized using OpenMP platform. The algorithm proposed ensures the correctness of the program. It performs the required parallelization without post execution analysis, which avoids both execution of code and monitoring of resources accessed by the program.
Keywords :
C language; application program interfaces; parallel programming; program control structures; source code (software); C code; OpenMP platform; automatic parallelization; automatic program parallelization; computing device performance improvement; for-loops; manual redesign; parallel computing platforms; parallel program development; performance gain; processing units; program correctness; serial execution; Algorithm design and analysis; Arrays; Computational modeling; Instruction sets; Multicore processing; Parallel processing; Reactive power; Automatic Parallelization; OpenMP; computation cost model; for loops;
Conference_Titel :
Advance Computing Conference (IACC), 2015 IEEE International
Conference_Location :
Banglore
Print_ISBN :
978-1-4799-8046-8
DOI :
10.1109/IADCC.2015.7154686