Silicon-compatible bulk-type compound junctionless field-effect transistor

Junctionless field-effect transistor (JLFET) is an attractive electronic device due to its simpler process architecture without concerning about thermal budgets in forming source and drain (S/D) junctions. JLFETs with silicon (Si) channel have been explored in many aspects [1-2], but they are not cost-effective since they need expensive silicon-on-insulator (SOI) substrate for electrical isolation of a device. In this work, a Si-compatible bulk-type compound JLFET is introduced and characterized by two-dimensional (2D) simulation [3]. Compound JLFET can be used as a core element in the driving circuits for integrated biosensors and photonic systems based on the compound semiconductors. Fig. 1(a) and (b) compare the material compositions of the conventional and the proposed JLFETs. The channel material is n⁺ gallium arsenide (GaAs) grown on Si substrate with a thick enough buffer layer of p⁺ germanium (Ge) for an n-type FET. The GaAs channel is epitaxially grown on Ge buffer layer with little lattice mismatch (Fig. 2). Also, GaAs and Ge have a large energy bandgap offset, which enables a self-isolation by effectively blocking leakage paths between the channel and substrate at any operation conditions. The simulated energy band diagrams with inserted schematics under various conditions are shown in Fig. 3(a) through (d). This genuine feature of self-isolation gets the device evolved into a vertical structure (which is suitable for surrounding gate) with one of the GaAs S/D junctions grown on Ge buffer. The gate oxide thickness (T_ox), physical gate length (L_G), and channel thickness (T_ch) of the simulated device in Fig. 3 were 1 nm, 40 nm, and 20 nm, respectively. The buffer layer and channel doping concentrations (N_BF, N_ch) were N_BF = 3×10¹⁷ cm^-3 and N_ch = 1×10¹⁸ cm^-3. A metal gate with workfunction of 4.33 eV - as used throughout the works. It is confirmed that leakages by band-to-band tunneling of Ge valence electrons with a high drain voltage (V_DS) and by hole current with a negative gate voltage (V_GS) are effectively blocked by the bandgap offsets between n⁺ GaAs and p⁺ Ge. The doping concentrations (for buffer layer and channel) and the channel thickness were controlled to examine their effects on device performance. Fig. 4(a) through (c) shows the I_D-V_GS curves and direct-current (DC) parameters of the proposed JLFET with different N_BF´s at T_ch = 20 nm and N_ch = 1×10¹⁸ cm^-3. Threshold voltages (V_th´s) were extracted at a constant drain current of I_D = 10^-6 A/μm in the saturation region, V_GS = V_DS = 1.0 V. Higher N_BF steepens the subthreshold slope (SS) but may have an upper limit near 3×10¹⁷ cm^-3 for on-state current (I_on) no less than 100 μA/μm reducing the mobility degradation [4]. The effects of N_ch are demonstrated in Fig. 5(a) through (c) (N_BF = 3×10¹⁷ cm^-3, T_ch = 20 nm). I_on shows a monotonic increase with N_ch but it is noticeable that there is an optimum value in I_on/I_off ratio near N_ch = 1×10¹⁸ cm^-3. The effects of T_ch were also investigated (Fig. 6). Although higher I_on is expected as T_ch gets thickner, the switching characteristics are degraded. T_ch can be optimized in terms of SS and I_on/I_off, which leads to 20 nm as the appropriate value.