A 1 V 0.9 mW at 100 MHz 2 k/spl times/16 b SRAM utilizing a half-swing pulsed-decoder and write-bus architecture in 0.25 /spl mu/m dual-Vt CMOS

Author

Mori, T. ; Amrutur, B. ; Mai, K. ; Horowitz, M. ; Fukushi, I. ; Izawa, T. ; Mitarai, S.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

354

Lastpage

355

Abstract

The main limitation resulting from reducing signal swings is reduction in gate overdrive at the receiving transistor leading to delay penalty. This design overcomes this using positive and negative half-swing signals on high-capacitance predecode lines so active decode circuits see a full gate-overdrive, while reducing decoder power. The half-Vdd supply is generated internally with high efficiency using charge-recycling between positive and negative half-swing signals. SRAM architecture and decoder organization are described.

Keywords

SRAM chips; 0.25 micron; 0.9 mW; 1 V; 100 MHz; 32 kbit; SRAM; active decode circuits; charge-recycling; decoder organization; decoder power; delay penalty; dual-Vt CMOS; gate overdrive; half-swing pulsed-decoder; high-capacitance predecode lines; receiving transistor; write-bus architecture; Decoding; Delay; MOS devices; MOSFETs; Noise figure; Noise reduction; Pulse circuits; Random access memory; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672522

Filename

672522