Investigation of vertical type single-electron transistor with sidewall spacer quantum dot

Modern VLSI technology has been developed with continuous scaling of MOSFET. However, as MOSFET has been scaled down, a lot of critical issues have risen and resulted in a considerable degradation of individual devices [1]. On the other hand, owing to its periodic on/off characteristic, single-electron transistor (SET) attracts attention with its promising performance. But, in general, fabricating SET, silicon-on-insulator (SOI) wafers have been used for their leakage current through buried oxide (BOX) on the substrate region [2]. However, in this paper, we propose a vertical structure that is fabricated on a bare wafer, not on a SOI wafer, and the fabrication process with which small size of a quantum dot (QD) can be formed more easily than previous works [1][3]. Since the smaller QD a SET has, the better operation characteristic it has at room temperature (RT), the characteristic of the SET device can be observed more clearly than previous works with the simple process to downsize a QD.