An N-channel graded-junction lateral diffused MOS transistor in 0.18μm low-power logic CMOS process

Lateral Diffused MOS(LDMOS) transistors are widely used in High-Voltage(HV) applications, such as embedded Non-Volatile Memory(eNVM)[1], smart power management[2], display drivers[3] and automotive applications. They can be fabricated under various manufacturing processes such as standard CMOS technology, Bipolar-CMOS-DMOS(BCD) technology, High-Voltage CMOS technology and Silicon-On-Insulator(SOI) technology. For commercial and integration considerations, it is desirable to develop LDMOS transistors in a cheap and available process compatible with standard CMOS process. The operating voltage of such low-cost LDMOS is several tens of volts. In less-advanced i.e. micron process era, REduced SURface Freld(RESURF) technology [4] and LOCal Oxrdatron of Srhcon(LOCOS) are applied to implement LDMOS transistors with standard CMOS process[5]. However, as the dominant process has entered deep sub-micron even nanometer scale, the fabrication technology has a great change e.g. thinner gate oxide, higher doping concentration and Shallow Trench Isolation(STI) replacing LOCOS as the thick field oxide. Therefore, novel and cheaper LDMOS transistors which can be embedded into the advanced standard CMOS process are required.