DocumentCode
3100579
Title
A 833 Mb/s 2.5 V 4 Mb double data rate SRAM
Author
Park, H.-C. ; Yang, S.-K. ; Jung, M.-C. ; Kang, T.-G. ; Kim, S.-C. ; Sohn, K.-M. ; Bae, D.-G. ; Kim, S.-S. ; Kim, K.-H. ; Sohn, B.-S. ; Kim, H.-S. ; Byun, H.-G. ; Shin, Y.-S. ; Lim, H.-K.
Author_Institution
Samsung Electron. Co. Ltd., Kiheung, South Korea
fYear
1998
fDate
5-7 Feb. 1998
Firstpage
356
Lastpage
357
Abstract
A double-data-rate (DDR) SRAM overcomes the limitation of a single-data-rate (SDR) SRAM. The main features are an auto-tracking bitline scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, a two bit pre-fetched operation, and strobe clocks synchronized with the output data to guarantee CPU data-validation time.
Keywords
SRAM chips; 2.6 V; 4 Mbit; 833 Mbit/s; CPU data-validation time; auto-tracking bitline scheme; core cycle time; current reduction; double data rate SRAM; dual-rail reset dynamic circuit; high-speed transfer characteristics; noise immune circuit; strobe clocks; two bit pre-fetched operation; Pulse circuits; Random access memory; Solid state circuits; Space vector pulse width modulation; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-4344-1
Type
conf
DOI
10.1109/ISSCC.1998.672524
Filename
672524
Link To Document