Low energy routing platforms for optical interconnects using active plasmonics integrated with Silicon Photonics

Power consumption and bandwidth of electronics appear as the main set of technology barriers in next-generation Data Center and High-Performance Computing (HPC) environments. The limited capacity and pitch lane of electrically wired interconnects require the development of new disruptive technologies to cope with the massive amount of data moving across all hierarchical communication levels, namely rack-to-rack, backplane, chip-to-chip and even on-chip interconnections. Plasmonics comes indeed as a disruptive technology that enables seamless interoperability between light beams and electronic control signals through the underlying metallic layer, providing thereby an inherent energy-efficient platform for merging broadband optical links with intelligent electronic processing. In ICT PLATON project we are aiming to the exploitation of plasmonics for the demonstration of novel hybrid Si-plasmonic router prototypes for chip-to-chip and on-chip interconnection, starting with a 2×2 WDM-traffic router with up to 640 Gb/s capacity and proceeding to a 4×4 router with up to 1.12 Tb/s throughput. In this article, we will present preliminary results of a 2×2 Si-plasmonic router that employs two 8:1 Si-ring-based multiplexers followed by a novel hybrid Si-plasmonic Mach Zehnder Interferometer switch with a record low power x time constant product.