MLP neural network implementation and integration in CMOS technology

The paper focus on the behavior of the NN MLP predistorter when real adders or multipliers generate impairments integrated in CMOS technology. Simulations show that the analog NN predistorter reaches always very good performances even with severe voltage offsets at the input of the different MLP integrated elements. For satellite communications, the on board high power amplifier is a highly nonlinear amplifier. Nonlinearities of CMOS implemented multipliers adders and impairments of integrated hyperbolic tangent are taken into account by the learning algorithm and, also, no significant peformance degradation is obtained. The microelectronics aspects of the MLP integration are also presented.