VLSI development of a global memory interface controller

A high-speed global bus chip used for interprocessor communications is developed. This 2.0 μm CMOS standard cell integrated circuit is targeted for use in digital signal processing (DSP) applications where global memory resources are required. The global memory interface controller (GMIC) contains both a bus arbitration unit to prevent bus contention and a memory controller to access the addressed memory location. The bus controller unit provides access to global memory resources for up to nine microprocessors. The microprocessor interface can be configured to be synchronous or asynchronous. Several error detection features are designed into the global bus. An internal watchdog timer monitors the health of the global bus. Parity error detection monitors data integrity as bus transactions occur. The memory controller is a versatile design that permits integration of the global bus into many different memory architectures. Each GMIC connected to the global bus contains one kiloword (16 bits) of internal static RAM