An efficient adiabatic charge-recovery logic

We propose a novel dual-rail energy efficient adiabatic charge recovery logic. We completely eliminate nonadiabatic loss during the charge phase, but allow partial reversibility only at nodes with small capacitance, in order to keep the reversibility overhead low. We apply transistor size optimization for a given frequency to alleviate the problem of increasing energy loss at higher operating frequencies. In the case of the nodes with high capacitance, a recovery path is introduced to provide complete charge recovery. The simulation on test circuits with the threshold voltage of 0.8 V showed 34% power reduction on average with complete recovery over the already optimally sized circuit