Modeling the floating-body-effect-related transient behavior of 40nm PD SOI NMOS device via the SPICE bipolar/MOS model

Floating body may cause effects on the performance of a PD SOI MOS device [1]. The floating-body-related transient behavior of a PD SOI NMOS device due to the function of the parasitic bipolar device has been reported [2]. In this paper, the modeling of the floating-body-effect-related transient behavior of a 40nm PD SOI NMOS device via the SPICE bipolar/MOS model is presented. Fig. 1 shows the SEM cross section of the 40nm PD SOI NMOS device under study. As shown in the figure, a thin film of 70nm is above a buried oxide of 145nm. The effective channel length is 40nm and the gate oxide thickness is 1.5nm. Experimental measurement, 2D simulation and the modeling via the SPICE bipolar/MOS model have been used to conduct the study. As shown in Fig. 2, the floating-body-effect-related transient behavior of the PD SOI NMOS device could be characterized using the SPICE bipolar/MOS model implemented in Verilog on the ADS platform, which is a combination of an MOS device with a bipolar device accounting for the function of the parasitic BJT in the device. Using the SPICE bipolar/MOS model for transient analysis, in addition to the displacement currents due to C_sg/C_dg, the drain current of the PD SOI NMOS device is composed of the surface channel current (I_ch), the hole current (I_h) generated by the impact ionization (II) in the high electric field region and the collector of the parasitic bipolar device (I_c). The base current (I_b) of the parasitic bipolar device comes from a portion of the II current (kI_h). The source current (IS) is composed of the channel current (I_ch), the remaining portion of the II current ((1-k)I_h) and the emitter current (I_E) of the parasitic bipolar device. A portion of the collector current (k´I_C) goes to the high electric field region, also triggering II. For the parasitic bipolar device, Gummel-Poon model has been adopted fo- transient analysis. Using the SPICE bipolar/MOS model, the floating-body-effect-related transient behavior of the 40nm PD SOI NMOS device could be analyzed. Fig. 3 shows the drain current of the 40nm PD SOI NMOS device during the turn-on transient, biased with V_D=2V and a voltage step from 0V to 2V imposed at the gate with a rise time of (a) 10ns and (b) 100ns, based on the SPICE bipolar/MOS model, 2D simulation results and measured data. As shown in the figures, the SPICE bipolar/MOS model could predict the drain current turn-on behavior accurately as verified by the 2D simulation results and experimentally measured data. As shown in the figures, the collector/emitter current of the parasitic bipolar device, which occupies a substantial amount of the drain current, could not be neglected. As indicated in Fig. 2, the II region and the parasitic bipolar device are the key factors in determining the floating-body-effect-related transient behavior of a PD SOI MOS device. Considering the displacement current effects from C_sg/C_dg, Fig. 4 shows the multiplication factor of the II region and the current gain of the parasitic bipolar device in the 40nm PD SOI NMOS device during the turn-on transient, biased with V_D=2V and a voltage step from 0V to 2V imposed at the gate with a rise time of (a) 10ns and (b)100ns, based on the SPICE bipolar/MOS model and 2D simulation results. As shown in the figure, in the gate ramp-up period, the multiplication factor decreases due to the smaller post-saturation region as the gate voltage increases. In the initial ramp-up period, the current gain of the parasitic bipolar device is small, indicating that the BJT is not turned on yet. In the final stage of the gate ramp-up period, the BJT suddenly turns on. From the figures, the SPICE bipolar/MOS model could predict the behavior of the multiplication factor of the II region and the current gain of the parasitic bipolar device closely as verified b