Analysis and simulation of a 45nm high-K/metal PD-SOI DTMOS under forward bias

Author

Jimenez-P, Abimael ; Ambrosio-L, Roberto C. ; Martinez-P, Carlos A. ; Monfil-L, Karim ; Munoz-G, Jose A. ; Blanco-G, Zurika I.

Author_Institution

Electr. & Comput. Eng. Dept., Univ. Autonoma de Ciudad Juarez, Ciudad Juárez, Mexico

fYear

2011

fDate

7-9 Dec. 2011

Firstpage

1

Lastpage

2

Abstract

As effective gate length and gate oxide thickness in Metal-Oxide-Semiconductor (MOS) transistors are aggressively scaled down for higher performance and circuit density, the levels for gate leakage current [1-2], standby power consumption [1-2] and gate oxide reliability [3] are degraded. Therefore, now hafnium dioxide (HfO₂) is being incorporated into the gate stack of silicon based MOSFETs.

Keywords

MOSFET; elemental semiconductors; hafnium compounds; high-k dielectric thin films; leakage currents; low-power electronics; semiconductor device reliability; silicon-on-insulator; circuit density; forward biasing; gate leakage current; gate length; gate oxide reliability; gate oxide thickness; hafnium dioxide; high-K-metal PD-SOI DTMOS simulation; metal oxide semiconductor transistors; silicon based MOSFET; size 45 nm; standby power consumption; Electric potential; Hafnium compounds; Leakage current; Logic gates; MOSFETs; Mobile communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium (ISDRS), 2011 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4577-1755-0

Type

conf

DOI

10.1109/ISDRS.2011.6135370

Filename

6135370