CPU dynamic thermal management via thermal spare cores

Adding cores to CPU chip increases its power density and leads to thermal throttling due to cooling limitations. Thermal spare cores (TSC) is proposed as new technique for dynamic thermal management (DTM). Our objective is to avoid thermal throttling and ensure stable CPU performance. Towards this objective, thermal model of IBM Power 4 CPU chip contains 8 cores implemented as proof of concept. TSC higher potential expected with CUP chip having higher number of cores under thermal constraints. In the near future we will be able to add dozens of cores to CUP chip; while we will not be able to activate them all simultaneously due to air cooling limitations and thermal throttling.