DocumentCode :
3102037
Title :
Experimental techniques for thermo-mechanical design in silicon validation platforms
Author :
Mohammed, Rahima K. ; Xia, Yi ; Pang, Ying-Feng ; Prabhugoud, Mohanraj ; Sahan, Ridvan A.
Author_Institution :
Intel Corp., Santa Clara, CA
fYear :
2009
fDate :
15-19 March 2009
Firstpage :
164
Lastpage :
171
Abstract :
Validation platforms are used to validate processors/chipsets to ensure Intel providing world-class quality and reliable products. In this paper, experimental methodologies of thermal, mechanical, acoustics, shock and vibration and ergonomic tests are demonstrated. These tests are essential to enable the boot-out-of-the-box model with increased complexities of the platforms while meeting the budget and schedule. Component level thermal testing data are correlated with CFD simulations to provide guidance for system simulations. The choice of second level thermal interface material (TIM2) was implemented using the detailed thermo-mechanical test data. Next, the acoustic tests are performed to meet acoustic safety requirements and to implement fan control to minimize system noise. Structural tests validated the retention designs based on finite element (FE) analyses. The packaged system level shock and vibration tests demonstrated the ability of the packaged system to avoid damages during shipping. Ergonomic chassis lifting tests illustrated in this paper assist to meet safety and ergonomic requirements for validation platforms. The experimental results guide the thermo-mechanical design decisions for validation platforms during the development and deployment phases. The work presented in this paper will serve as a guideline to support future thermo-mechanical designs of validation platforms.
Keywords :
computational fluid dynamics; electronics packaging; finite element analysis; thermomechanical treatment; vibrations; CFD simulations; acoustic safety requirements; acoustic tests; component level thermal testing; ergonomic chassis lifting tests; ergonomic tests; fan control; finite element; processor-chipsets; silicon validation platforms; structural tests; system level shock; system simulations; thermal interface material; thermomechanical design; vibration tests; Acoustic testing; Electric shock; Ergonomics; Packaging; Processor scheduling; Safety; Silicon; System testing; Thermomechanical processes; Vibrations; CFD; TIM; Validation platform; acoustic; ergonomic; experimental methodology; mechanical design; shock; thermal design; vibration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Thermal Measurement and Management Symposium, 2009. SEMI-THERM 2009. 25th Annual IEEE
Conference_Location :
San Jose, CA
ISSN :
1065-2221
Print_ISBN :
978-1-4244-3664-4
Electronic_ISBN :
1065-2221
Type :
conf
DOI :
10.1109/STHERM.2009.4810759
Filename :
4810759
Link To Document :
بازگشت