Hardware Architecture to Realize Multi-layer Image Processing in Real-time

Visual data with appropriate processing has very important information for many robotic applications. Usually, people use digital computer to do the image processing, but for complex or copious algorithms, due to the architecture of present CPU-based computing system, it is very time consuming and resource wasting to do these kinds of process. In this paper, we focus on the crucial case - image algorithms with multi-layer processes. In this kind of algorithms, the following process always need to wait the result from the previous step and access the memory very frequently, which cause the timing delay and resource grabbing in general CPU-based system. In order to solve this problem, first we go deep into the data flow in multi-layer image processing. We observe that it has many parallel and pipeline properties without waiting for some unnecessary delay, and fortunately, these properties exactly match with the characteristics of hardware design. For this reason, we propose a novel hardware architecture called visual pipeline to overcome these problems. The combination of the concepts from parallel and pipeline properties in hardware design are used, and finally we use FPGA to implement our architecture. To verify our hardware design, we use multi-scale Harris corner detector as the example, which is also a multi-layer process. Finally, we can show the result running in real-time of multi-layer image processing.