Impact of temperature-dependent die warpage on TIM1 thermal resistance in field conditions

The evolution of microprocessor architectures has driven semiconductor manufacturers making transition from ceramic to organic package substrate technology in order to take full advantage of the silicon advances. However, large mismatch in coefficients of thermal expansion (CTE) between silicon die and organic substrate results in significant die/package warpage that adversely impact the package´s thermomechanical performance during assembly processes and longterm reliability in use conditions. In contrast to the extensive studies in various mechanical failures, little research effort has been pursued in the investigation of impacts from die warpage on package thermal performance and TIM degradations, mainly due to the limitation of existing steady-state and transient thermal characterization techniques. This work explores the application of frequency-domain thermal impedance measurement technique in study of impact on thermal resistance at TIM1 level from temperature-dependent die warp behavior in field conditions. Hysteresis loop of thermal impedance at TIM1 level as a function of junction temperature is observed which indicates the TIM delamination due to its failure to accommodate the temperature-dependent die warpage. Evaluations of TIM candidates with different bond-line thicknesses (BLT), TIM curabilities, and die sizes suggest that optimizations of BLT are required in order to meet both mechanical and thermal performance requirements.