Uniformity improvement by optimization of switching interface in bi-layer unipolar RRAM structure for low power new memory application

RRAM is very promising due to many fascinating advantages as follows; fast writing/reading time, low programming power and multi bit storage for high density up to tera bit memory are possible [1]. But it is very difficult to satisfy all best resistive switching characteristics. There is a trade-off between reset current (I_RESET) and forming voltage (V_FORMING) in single layered cell structure as shown in fig. 1 (a). Fig. 1 (b) shows the initial resistance (R_INITIAL) as a function of reset resistance (R_RESET) and set resistance (R_SET) by using our fabricated NiO based unipolar RRAM cell. We have reported that V_FORMING increases if R_INITIAL is high enough, therefore it proves that R_INITIAL needs to be lowered in order to lower operating condition [2]. However there is also a trade off. If R_INITIAL is sufficiently low, sensing margin which means reset/set resistance ratio is also reduced. So, new ideas for satisfying both resistive switching conditions are needed. Figure 2 shows the typical I-V curves of forming (a) and reset/set switching (b) based on single layered unipolar RRAM structure by using RCB model [3] and figure 3 shows the illustration of bi layered RRAM cell structure. Lower layer (2^ND resistive layer) is acting as forming assistance layer for low power consumption. Upper layer (1^ST resistive layer) is used for controlling reset/set switching. Because resistive switching occurs at cell interface, interface engineering is very critical for improving resistive switching uniformity. Figure 4 illustrates the detailed tested metal - insulator-metal (MIM) cell structure. Charged particle which is source of CF path such as oxygen vacancy and metallic ion in resistive cell can be defined as conductive defect. Conductive defect fraction is varied from 0.05 (lower layer) to 0.025 (upper layer), respectively. Conductive defect fraction of referen- e cell is 0.05. The each layer rules and their actions for bi-layered RRAM cell structure are summarized in table 2. Figure 5 shows the statistical analysis of V_FORMING (a) and V_SET (b) characteristics with various cell conditions. Lower V_FORMING is addressed in single layered cell due to its larger amount of conductive defects, but in case of 5nm thickness of upper layer (split 1) cell, mean value of forming voltage (V_FORMING_μ) difference is only 0.26V.