Reliability test chips: NIST 33 and NIST 34 for JEDEC inter-laboratory experiments and more

Author

Schafft, Hany A.

Author_Institution

Semicond. Electron. Div., Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA

fYear

1997

fDate

13-16 Oct 1997

Firstpage

144

Lastpage

145

Abstract

Two reliability test patterns, NIST 33 and NIST 34, are being designed, and a third, NIST 36, is being planned to be used in a number of inter-laboratory experiments as part of the activities of the Metal Reliability Task Group of the EIA/JEDEC Committee JC 14.2 on Wafer Level Reliability. These chips will also be used for other tasks, many of which will provide additional characterization data in support of the JEDEC inter-laboratory experiments

Keywords

integrated circuit design; integrated circuit reliability; integrated circuit testing; standards; EIA/JEDEC Committee; JEDEC inter-laboratory experiments; Metal Reliability Task Group; NIST 33 reliability test chips; NIST 34 reliability test chips; NIST 36 reliability test chip; characterization data; reliability test chips; reliability test pattern design; wafer level reliability; Electrical resistance measurement; Electromigration; Electronic equipment testing; Isothermal processes; NIST; Semiconductor device reliability; Stress measurement; Thermal conductivity; Thermal stresses; X-ray diffraction;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 1997 IEEE International

Conference_Location

Lake Tahoe, CA

Print_ISBN

0-7803-4205-4

Type

conf

DOI

10.1109/IRWS.1997.660312

Filename

660312