LUT-based FPGA technology mapping for power minimization with optimal depth

Author

Li, Hao ; Wai-Kei Mak ; Katkoori, Srinivas

Author_Institution

Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA

fYear

2001

fDate

37012

Firstpage

123

Lastpage

128

Abstract

In this paper, we study the technology mapping problem for LUT-based FPGAs targeting power minimization. We present the PowerMap algorithm to generate a mapping solution to minimize power consumption while keeping the delay optimal. We compute min-height K-feasible cuts for critical nodes to optimize the depth and compute min-weight K-feasible cuts for noncritical nodes to minimize the power consumption of the mapping solution. We have implemented PowerMap in C and tested it on a number of MCNC benchmark circuits. Compared to FlowMap, a delay-optimal mapper, our algorithm reduces the power consumption by 17.8% and uses 9.4% less LUTs without any depth penalty

Keywords

Boolean functions; VLSI; circuit optimisation; field programmable gate arrays; logic CAD; low-power electronics; minimisation of switching nets; table lookup; LUT-based FPGA technology mapping; MCNC benchmark circuits; PowerMap algorithm; critical nodes; mapping solution; min-height K-feasible cuts; min-weight K-feasible cuts; noncritical nodes; optimal depth; power consumption; power minimization; Arthritis; Capacitance; Circuits; Delay estimation; Energy consumption; Field programmable gate arrays; Minimization methods; Programmable logic arrays; Semiconductor device modeling; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2001. Proceedings. IEEE Computer Society Workshop on

Conference_Location

Orlando, FL

Print_ISBN

0-7695-1056-6

Type

conf

DOI

10.1109/IWV.2001.923150

Filename

923150