Technique for reducing on-resistance of high-voltage drivers based on stacked standard CMOS

This paper presents a new technique for reducing on-resistance of high-voltage drivers, which are based on N-stacked standard CMOS. A theory to calculate gate voltages of HV-driver transistors to drive the maximum drain current for minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology for generating them is described. This concept is technology independent and compatible with scaled CMOS devices. The theory and circuit design are proved by simulating a 2-stack CMOS driver in 65-nm technology, demonstrating significantly improved rise and fall times of the driver, if compared to previous work.