Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs

Author

Kim, Dae Hyun ; Kim, Suyoun ; Lim, Sung Kyu

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2011

fDate

5-5 June 2011

Firstpage

1

Lastpage

8

Abstract

One of the most effective ways to deal with the area and capacitance overhead issues with through-silicon vias (TSVs) in 3D ICs is to reduce the size of TSVs themselves. Today, the diameter of the smallest TSV available is around 1 μm, and this is expected to reach sub-micron dimensions in a few years. This downscaling of TSVs requires research on the impact of nano-scale TSVs on the quality of 3D IC designs to provide academia and industry with the quantified effects. In this paper, we investigate, for the first time, the impact of nano-scale TSVs on the area, wirelength, delay, and power quality of today and future 3D IC designs. For our future process technology, we develop a 22nm standard cell and interconnect library. We also use four sets of TSV-related dimensions in our GDSII-level 3D IC layouts. Based on these resources, we present a thorough study on the impact of nano-scale TSVs on the design quality of today and future 3D ICs.

Keywords

cellular arrays; delays; integrated circuit interconnections; integrated circuit layout; nanoelectronics; three-dimensional integrated circuits; 3D IC design; GDSII-level 3D IC layout; TSV size reduction; TSV-related dimensions; delay; interconnect library; nanoscale through silicon vias; power quality; size 22 nm; standard cell library; wirelength; Capacitance; Delay; Inverters; Logic gates; Metals; Three dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

System Level Interconnect Prediction (SLIP), 2011 13th International Workshop on

Conference_Location

San Diego, CA

Print_ISBN

978-1-4577-1240-1

Type

conf

DOI

10.1109/SLIP.2011.6135435

Filename

6135435