Title :
Device design methodology and reliability strategy for deep sub-micron technology [DRAMs]
Author :
Divakaruni, Rama ; El-Kareh, Badih ; Tonti, William R.
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
Abstract :
This tutorial paper discusses device and process optimization techniques that may be employed in the design of current state-of-the-art bulk silicon DRAM technology. MOSFET performance and reliability issues are contrasted
Keywords :
DRAM chips; MOS memory circuits; MOSFET; circuit optimisation; integrated circuit design; integrated circuit reliability; DRAMs; MOSFET performance; MOSFET reliability; Si; SiO2-Si; bulk silicon DRAM technology; device design methodology; device optimization; device reliability strategy; process optimization; Boron; Degradation; Design methodology; Doping; High definition video; Hot carriers; Implants; MOSFET circuits; Random access memory; Threshold voltage;
Conference_Titel :
Integrated Reliability Workshop Final Report, 1997 IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-4205-4
DOI :
10.1109/IRWS.1997.660315
