Title :
GEEP: a low power genetic algorithm layout system
Author :
Holt, Glenn ; Tyagi, Akhilesh
Author_Institution :
Dept. of Comput. Sci., Iowa State Univ., Ames, IA, USA
Abstract :
In this paper we present GEEP, a genetic algorithm for low power standard-cell placement. GEEP reduces interconnect capacitance by an average of 20% over recursive min-cut area optimizing placement. It incorporates a number of heuristics to produce good placements fast relative to existing GAs, including a novel method for handling low population diversity. We tested GEEP on a suite of MCNC benchmarks and found this hybrid approach successful in producing good post-placement results in a reasonable number of generations
Keywords :
VLSI; cellular arrays; circuit layout CAD; genetic algorithms; integrated circuit interconnections; integrated circuit layout; logic CAD; GEEP; MCNC benchmarks; VLSI; genetic algorithm; heuristics; interconnect capacitance; low power standard-cell placement; population diversity; post-placement results; Capacitance; Circuit synthesis; Clocks; Computer science; Genetic algorithms; Integrated circuit interconnections; Logic devices; Personal digital assistants; Routing; Space technology;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.593180
