A distributed cache memory for multiprocessors based on the crossbar interconnection principle

A distributed cache memory scheme for shared-memory multiprocessor based on a modified crossbar interconnection network is described. It is shown that for any set of p memory addresses, where p is the number of processors, the same amount of memory requests may be serviced simultaneously. For cache hits, the architecture approaches the ideal model of the PRAM (parallel random access machine), in the sense that all processors have simultaneous access to shared memory. The operation protocol of the cache memory is discussed, and performance evaluations are presented