An improved ROM architecture for bubble error suppression in high speed flash ADCs

In high speed flash ADCs, the thermometer coded output of the comparators is converted to binary code by a thermometer-to-binary decoder using a ROM. The ROM is simple and straightforward to design but it requires bubble error correction/suppression circuitry. A novel ROM architecture suitable for high speed operation with bubble error suppression is described in this paper. An 800 MHz 6-bit flash ADC is designed and simulated to verify the performance of different ROM architectures. The proposed ROM architecture eliminates the need of gray encoded ROM as well as gray to binary conversion circuitry, hence reduces the complexity and enhances the performance.