High slew-rate, high gain operational amplifier driving large capacitive loads in a BiCMOS high voltage technology

Author

Boni, A. ; Togni, G. ; Morandi, C.

Author_Institution

Dipartimento di Ingegneria dell´´Inf., Parma Univ., Italy

Volume

1

fYear

1996

fDate

13-16 May 1996

Firstpage

403

Abstract

This paper describes the design and implementation of a high slew rate, high gain Operational Amplifier in a 3 μm high voltage BiCMOS process. A BiCMOS differential pair and an inverter gain stage with P-MOS cascode load is used in order to achieve a slew rate of about 50 V/μs and a DC open loop gain of 112 dB. A novel BiCMOS output buffer which can drive capacitive loads from 0 to 200 pF is introduced. A comparison between the proposed amplifier and two amplifiers available in the cell library of the used technology is presented: it demonstrates the excellent performance of the proposed amplifier in term of slew rate, capacitance driving capability, open loop DC gain and CMRR

Keywords

BiCMOS analogue integrated circuits; operational amplifiers; power integrated circuits; 0 to 200 pF; 112 dB; 3 micron; BiCMOS high voltage technology; CMRR; DC open loop gain; P-MOS cascode load; capacitive load; differential pair; inverter; operational amplifier; output buffer; slew rate; BiCMOS integrated circuits; Capacitance; Capacitors; Driver circuits; Operational amplifiers; Pulse width modulation; Pulse width modulation inverters; Rails; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrotechnical Conference, 1996. MELECON '96., 8th Mediterranean

Conference_Location

Bari

Print_ISBN

0-7803-3109-5

Type

conf

DOI

10.1109/MELCON.1996.551566

Filename

551566